NXP Semiconductors /MIMXRT1011 /FLEXRAM /DTCM_MAGIC_ADDR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DTCM_MAGIC_ADDR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DTCM_WR_RD_SEL_0)DTCM_WR_RD_SEL 0DTCM_MAGIC_ADDR

DTCM_WR_RD_SEL=DTCM_WR_RD_SEL_0

Description

DTCM Magic Address Register

Fields

DTCM_WR_RD_SEL

DTCM Write Read Select

0 (DTCM_WR_RD_SEL_0): When DTCM read access hits magic address, it will generate interrupt.

1 (DTCM_WR_RD_SEL_1): When DTCM write access hits magic address, it will generate interrupt.

DTCM_MAGIC_ADDR

DTCM Magic Address

Links

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